The present invention relates to a circuit arrangement with at least four transistors. Two of the four transistors are complementary to the remaining two transistors. The four transistors are suited in particular for use as a NAND gate.
In the development of new integrated circuit arrangements, there is a need for increased packing density. The realization currently takes place mostly in a planar silicon technology.
NAND gates are frequently-used logical elements of circuit arrangements. If at least one of two input voltage terminals of a NAND gate supplies a signal in the form of a voltage, a signal is likewise obtained at the output voltage terminal of the NAND gate. In K. Hoffmann, VLSI-Entwurf, Modelle und Schaltungen, Oldenburg 1990, page 365, a typical layout of a NAND gate is disclosed.
Smaller structural sizes in planar technology can be achieved if the optical lithography is replaced by electron beam lithography, whose resolution capacity is essentially better; see e.g. T. Mizuno, R. Ohaba, IEDM Techn. Dig., page 109, 1996. Since, however, electron beam lithography is slow, it does not appear suitable for use in semiconductor manufacturing, for economic reasons.
For the reduction of the surface of an MOS transistor, vertical transistors are examined. Since the channel length runs vertically in relation to a surface of a substrate, the surface of a vertical transistor can be smaller than the conventional planar transistors. A further reduction of the surface is obtained by reducing the channel width required for a particular current strength, in that the channel length is shortened. In L. Risch, W. H. Krautschneider, F. Hofmann, Vertical MOS-Transistor with 70 nm Channel Length, ESSDERC 1995, pages 101 to 104, vertical MOS transistors are described. For their manufacture, doped layers of alternating conductivity types are fashioned in the form of a layer sequence corresponding to source, channel, and drain, surrounded annularly by the gate dielectric and gate electrode.